1. Field of the Invention
The present invention generally relates to a phase-locked loop (PLL), and more particularly to a nested fractional-N PLL.
2. Description of Related Art
A phase-locked loop (PLL) is a control system that uses a negative feedback to generate an output frequency that is phase-locked to a reference frequency. The PLL is widely used in a variety of applications, such as synthesizing a stable frequency or recovering a signal from a communication channel. The ratio of the output frequency to the reference frequency of the PLL may be a whole number, or may be a mixed number that is the sum of a whole number and a fraction. The former is commonly known as an integer-N PLL or synthesizer, and the latter is commonly known as a fractional-N PLL or synthesizer. A delta-sigma synthesizer with a delta sigma modulator (SDM) is a popular one among various types of fractional-N synthesizers. Nevertheless, the SDM generates quantization noise that incurs output clock jitter. In order to alleviate the clock jitter effect, a capacitor with large capacitance (e.g., more than thousands of picofarads (pF)) may be used to filter the quantization noise, but at a cost of increased circuit area and power consumption.
For the reason that conventional PLL could not effectively reduce the clock jitter in the delta-sigma synthesizer, a need has arisen to propose a novel scheme for filtering quantization noise in an effective manner without substantively increasing circuit area.